An FPGA is a programmable logic device having an array of configurable logic blocks (CLBs) connected together via a programmable routing structure. A typical FPGA may have tens of thousands of CLBs, each CLB having a plurality of primitive logic cells such as AND gates, lookup tables, registers, etc. The CLBs may be interconnected in a variety of ways to implement a desired logic function.
FIG. 1 schematically shows a portion of an FPGA 100 having a plurality of CLBs 102 interconnected through a routing structure 104. Routing structure 104 is programmed to provide desired connections between CLBs 102 using configurable circuit elements, e.g., pass-transistors and/or multiplexers (MUXes), that are variously coupled between different transmission lines of the routing structure. Each configurable circuit element of routing structure 104 is controlled by a corresponding static random-access memory (SRAM) block (having one or more memory cells) such that desired connections in FPGA 100 are achieved by writing appropriate data into the SRAM blocks.
For example, FIG. 1 illustratively shows a programmable connection between an AND gate in CLB 102a and an AND gate in CLB 102z implemented using two pass-transistors 112a and 112b and a MUX 114. The gate nodes of pass-transistors 112a and 112b are controlled by an SRAM cell in an SRAM block 122a and an SRAM cell in an SRAM block 122b, respectively, and the one or more select lines of MUX 114 are controlled by one or more SRAM cells in an SRAM block 124. When the corresponding cell in SRAM block 122 has a binary “one”, the associated pass-transistor 112 is turned into an “on” state, thereby electrically connecting the transmission lines of routing structure 104 coupled to the source and drain of that pass-transistor. Alternatively, when that SRAM cell has a binary “zero”, pass-transistor 112 is turned into an “off” state, thereby electrically isolating those lines. Similarly, when the one or more cells in SRAM block 124 have a specific appropriate binary value, MUX 114 selects its input line connected to pass-transistor 112b, thereby electrically connecting that pass-transistor to the AND gate in CLB 102z. Alternatively, when SRAM block 124 has a different binary value, MUX 114 selects a different input line, thereby electrically isolating that pass-transistor from the AND gate.
Each memory cell in SRAM blocks 122 and 124 typically has four or six transistors arranged to form a bistable circuit, wherein one circuit state corresponds to the binary “one” and the other circuit state corresponds to the binary “zero”. For reliable operation of FPGA 100, the data stored in SRAM blocks 122 and 124 need to remain unchanged after the FPGA has been programmed because, as shown above, changes in the stored data may alter connections between the CLBs. These changes, in turn, might cause functional/processing errors in FPGA 100.
It is known that alpha particles present in ambient cosmic rays can cause a memory cell of an SRAM block to change its state upon a particle strike. This effect is known as a “soft error.” The problem of soft errors becomes more pronounced as the transistor size, with which FPGA circuit elements are implemented, decreases. For example, one of the contributing factors is that a relatively small capacitive charge of a relatively small transistor makes the transistor more susceptible to a state change due to the effect of the electrical charge generated in the alpha-particle wake. A representative prior-art solution to soft errors is to carry out frequent memory reads to detect and correct state changes. However, disadvantageously, frequent reading of SRAM blocks reduces the voltage level of internal nodes and slows down the general speed of the FPGA operation.